1. Field of The Invention
The present invention relates to a method for controlling a nonvolatile memory device having a memory region of four bits or larger in one memory cell sandwiched by a source and a drain.
2. Related Art
An NAND (not and) nonvolatile memory device having a plurality of memory regions and a plurality of counterpart control gates, which are all disposed between a source and a drain, is known in the conventional technology.
A type of NAND cell that conducts writing data by utilizing tunneling current is disclosed by Masaki Momodomi et al., in “An Experimental 4-Mbit CMOS EEPROM with a NAND-Structured Cell”, IEEE Journal of solid-state circuits, vol. 24, No. 5, 1989, pp. 1238 to 1243, and is also disclosed in Japanese Patent Laid-Open No. H5-129,564 (1993). In Japanese Patent Laid-Open No. H5-129,564, a nonvolatile memory device having a configuration that does not include an impurity diffusion layer provided among a plurality of memory regions (and control gates) is disclosed. FIG. 10 is a circuit schematic of a nonvolatile memory device described in Japanese Patent Laid-Open No. H5-129,564. A transistor Q1 includes a plurality of gate electrodes CG1 to CG8. One end of source/drain of a transistor Q2 is grounded, and another end is coupled to the transistor Q1. One end of a transistor Q3 is applied with an electrical voltage VDD, and another end is coupled to the transistor Q1.
Writing data on the nonvolatile memory device having such configuration by utilizing tunneling current is conducted as follows. When data is, for example, written on a gate electrode CG5, electrical voltages across a gate electrode AG1 of the transistor Q2 and gate electrodes CG1 to CG4 of the transistor Q1 are set to be low (at 0 V), providing a status of OFF. Further, electrical voltages across a gate electrode AG2 of the transistor Q3 and gate electrodes CG6 to CG8 of the transistor Q1 are set to be high (at 5 V), providing a status of ON. Then, a higher voltage of 20 V is applied to the gate electrode CG5 for a certain time to cause a Fowler-Nordheim (FN) current injection, thereby injecting electron into a nitride film in vicinity of this electrode. This process achieves data stored in the control electrode CG5. Since the gate electrode AG1 and the gate electrodes CG1 to CG4 are the status of OFF in this occasion, no through current flows from the power supply to the ground.
On the other hand, a type of NAND cell of a configuration having no selector gate is disclosed by Fujio Masuoka et al., “New Ultra High Density EPROM and Flash EEPROM with NAND Structure Cell”, IEDM 87, 1987, pp. 552 to 555. Impurity diffusion layers are provided among a plurality of memory regions (and control gates) of such cell. Further, this cell is composed of four memory transistors, which are connected in series, and each of these memory transistors has a structure, in which a floating gate (FG) (made of poly Si film) is buried in a gate oxide film of a negative polarity metal oxide semiconductor (NMOS) transistor. Writing data on the cell having such configuration is conducted by injecting a channel hot electron (CHE) through the following procedure. First of all, an electrical voltage of 9 V is applied to a bit line coupled to a memory transistor located in one end thereof. A memory transistor located in another end is grounded. Here, an electrical voltage of 10 V is applied to a control gate, which is a counterpart to a memory region selected as a data-written medium, and higher electrical voltage of 20 V is applied to the other control gate, which is a counterpart to a memory region that is not selected as a data-written medium. By such application of higher electrical voltage, the electrical voltage that has been applied to the bit line is applied to an impurity-diffused regions in each side of the selected control gate via a inversion layer formed at each of the memory transistor by so-called virtual-drain-effect and a hot electron is generated in a channel region located under the selected control gate, and eventually an electron is injected into a floating gate located under the control gate.
Further, a storage cell that is configured to include a control gate and a floating gate, which are disposed in series between a source and a drain, is disclosed in M. Kamiya et al., “EPROM CELL WITH HIGH GATE INJECTION EFFICIENCY”, IEDM 82, 1982, p. 741 to 744. In such storage cell, the control gate and the floating gate are arranged in this order between the source and the drain, and a higher voltage is applied to the drain and a lower voltage is applied to the source, and further a higher voltage, which is higher than the voltage applied to the control gate, is applied to the floating gate, so that a hot electron generated in the higher electric field region in vicinity of a boundary between the control gate and the floating gate is injected to the floating gate from the side of the source (source-side-injection or perpendicularly accelerating channel (PAC) injection).
On the other hand, Japanese Patent Laid-Open No. 2003-17,600 discloses a nonvolatile memory device including a first and a second memory cells, which are connected between a pair of bit lines. It is described that, when one of the first and the second memory cells of such nonvolatile memory device functions as a data cell for storing data, the other functions as a selected cell.
In the meantime, a miniaturization of nonvolatile memory devices is generally expected in the industry, and in such circumstances, when the configuration of utilizing FN current injection is employed, it is necessary to provide the gate electrode AG1 of the transistor Q2 or the gate electrode AG2 of the transistor Q3, as shown in FIG. 10 for example, in addition to providing the gate electrodes CG1 to CG8 corresponding to respective memory regions, causing a problem of opposing the requirement of miniaturization.
Consequently, the present inventors have investigated a process for writing data onto a target memory region via a CHE injection. Although the above-described Masuoka et al discloses a technology for writing data on the memory cell by utilizing the CHE injection, the configuration of Masuoka et al. includes additional impurity-diffused regions respectively formed between each of the memory regions. In this regard, miniaturization of the cell is obstructed. In addition, the method for injecting electron disclosed by Masuoka et al. utilizes virtual-drain-effect, and thus, when the size of the cell is reduced to have shorter channel-length of each bit, leakage current due to a punchthrough is increased. In addition, since the injection of electron to the memory region is implemented for larger area in an ordinary CHE injection, it is difficult to selectively inject electron only in the target memory region in this process, when the size of the gate length of the control gate is reduced. In this regard, miniaturization of the cell can not be achieved by employing the process of Masuoka et al.
On the other hand, when the source-side injection disclosed by M. Kamiya et al., “EPROM CELL WITH HIGH GATE INJECTION EFFICIENCY”, IEDM 82, 1982, p. 741 to 744 is employed, an electron can be selectively injected within a desired very small region of the memory region. When only two control gates between the source and the drain are employed as in the configuration of the aforementioned Masuoka et al., the source-side injection can be achieved by applying an appropriate electrical voltage to the two control gates, so that these control gates function as a gate for selecting the target memory region for writing data and a gate for controlling a level of electron current, respectively.
Nevertheless, when number of control gates disposed between the source and the drain is further increased in the conventional configuration, no countermeasure for injecting electron by the source-side injection process has not been examined.